The present invention relates to processes for manufacturing cathode ray tubes. In particular, the present invention pertains to a novel method for implementing a six mask process for fabricating a cathode for use in a cathode ray tube.
The flat panel or thin cathode ray tube (CRT) is a widely and increasingly used display device. Thin CRTs, such as the ThinCRT(trademark) of Candescent Technologies Corp., San Jose, Calif., are used in desktop and workstation computer monitors, panel displays for many control and indication, test, and other systems, and television screens, among a growing host of other modern applications.
Thin CRTs work on the same basic principles as standard CRTs. Referring to Conventional Art FIG. 1, beams of electrons E are fired from negatively-charged electrodes, e.g., cathodes C, through an accelerating potential AV in an evacuated glass tube T. The electrons E strike phosphors Ph in front of an aluminum (Al) layer anode A at the front of the tube T, causing them to emit light L, which creates an image on a glass screen GS. One difference is that, in place of the conventional CRT""s single large cathode are millions of microscopic electron emitters EE spread across the cathode at the back of the thin CRT, each firing a small beam of electrons E toward the phosphor Ph coated screen GS.
These emitters EE use cold cathode technology, which consumes only a small fraction of the power used by the traditional CRT""s hot cathode. It is estimated that a 14.1 inch thin CRT, such as the ThinCRT(trademark) color notebook display, will use less than 3.5 watts, over an order of magnitude less than a typical conventional CRT of roughly 80 watts, and even less than liquid crystal displays (LCD), such as AMLCDs, at equivalent brightness. Referring to Conventional Art FIG. 2, millions of electron emitters EE on the thin CRT cathode C release electrons E that are accelerated towards the phosphor Ph on the thin CRT faceplate GS which, when struck, emits light towards the viewer. Ceramic spacers mechanically support the thin CRT structure, containing high vacuum between the anode A and cathode C, against the imploding forces of ambient atmospheric pressure AAP.
The manufacture of a thin CRT involves a number of specialized, complex technical and industrial fabrication processes. One such process is the formation of the cathode element of the thin CRT. Cathode fabrication processes involve a number of steps, some of them familiar in other aspects of modern electronic manufacturing. However, cathodes for thin CRTs have relatively complex designs, as well as certain unique structural features and material compositions, which tend to complicate their manufacture, in accordance with conventional methods.
With reference to Conventional Art FIG. 3, some of the details of the thin CRT design are described. A dielectric 1 covers a patterned resistor layer 2. Both are disposed over a glass cathode substrate 3, onto which is arrayed row metal 4 and an emitter array 5, shown in detail in blown up internal Figure 3.1. A single cathodic emitter cone and gate hole micro-array 6 is depicted in detail in blown-up internal Figure 3.1.1. Column metal 7 is arrayed over the row metal 4. Column metal 7 and row metal 4, together, form individually addressable cathodic locales at their intersections. A focusing grid 8 disposed upon mechanically supportive walls 9 allow electron beams (e.g., electron beams E; Conventional Art FIG. 1) to be focused onto individual pixels, such as pixel 13, which is depicted in the present Figure as xe2x80x9conxe2x80x9d (the other pixels therein are depicted as xe2x80x9coffxe2x80x9d). Pixels, such as pixel 13, form a screen with an anodic Al layer 12 (corresponding to Al anode A; Conventional Art FIGS. 1, 2) and a contrasting blackened matrix 11, all disposed upon a faceplate glass 14 (corresponding to glass screen GS; Conventional Art FIGS. 1, 2).
With reference to Conventional Art FIG. 4, low voltage, planar cold cathodes C are used in thin CRTs. These cathodes contain many individual electron emitters 55 (corresponding to electron emitters EE; Conventional Art FIGS. 1, 2 and cathodic emitter cone and gate hole micro-array 6; Conventional Art FIG. 3), which are addressable with low-voltage, inexpensive drivers via row and column conductors, such as column metal 7 and row metal 4, together forming individually addressable cathodic locales at their intersections. These cathodes exhibit high spatial and temporal uniformity, have a very high degree of emitter redundancy, and can be produced at low cost, relative to other display technologies, such as LCDs and conventional bell tube CRTs.
One such thin CRT cathode is the Spindt Cathode 55, a micron-size metallic cone centered in a roughly micron diameter hole through a top metal and insulator thin films, shown in detail in blown up internal Figure 4.1. The tip of the cone lies in the plane of the top metal (xe2x80x9cgatexe2x80x9d) film and is centered in the gate hole. The cone has a sharp tip; thus a voltage differential between the cone and gate film causes electrons to emit from the cone tip into the vacuum characterizing an accelerating potential (e.g., AV; Conventional Art FIG. 1). Several approaches for fabricating cold cathodes exist.
One conventional process of fabricating 1 micron scale Spindt emitters 55 requires several relatively slow and costly photolithographic steps. Additionally, at 1 micron gate widths, more expensive integrated circuit drivers rated at 80 volts are needed. This voltage range results in a high power consumption that is unacceptable for portable applications. Spindt cathode power and cost limitations may be overcome if the device geometry is reduced from micron to nanometer-scale, e.g., less than 0.15 microns, and if faster non-photolithographic patterning techniques are employed.
Resulting cold cathode emitters are fabricated over large glass substrates. One type of cold cathode plate is constituted by a matrix array of patterned, individually addressable, orthogonal row and column electrodes (e.g., column metal 7 and row metal 4 together form cathodic locales at their intersections). The intersection (e.g., cross-over area) between each row and column defines a sub-pixel element, at which a very dense array of cold cathode emitters is formed. Referring to Conventional Art FIG. 5, row metal conductors (e.g., row metal 4; Conventional Art FIGS. 3, 4) and column metal conductors (e.g., column metal 7; Conventional Art FIGS. 3, 4) are electrically couplable from exposed conductors in the M1 areas 5M1 and the M2 areas 5M2, respectively. Active area 5A contains the actual cathodes (e.g., cathodes 55; Conventional Art FIGS. 3, 4).
Nanometer scale emitters currently allow up to 4,500 emitters to be located at each sub-pixel. This high degree of redundancy results in a defect tolerant fabrication process because a number of non-performing emitters can be tolerated at each sub-pixel site. From a manufacturing cost standpoint this is significant because the one very small element, the cathode emitter, has large redundancy. The remaining device features, such as the rows and columns (e.g., column metal 7 and row metal 4, together, forming individually addressable cathodic locales at their intersections), are relatively low resolution (on the order of 25 to 100 microns) which are compatible with relatively low cost (e.g., non-stepper lithography-based and high yielding) manufacturing processes.
Conventional cathode fabrication processes for thin CRT manufacture involve varying sequences of substrate formation and treatment, photoresistive patterning and etching, layer deposition, structure formation, other etching, cleaning, and related steps. The level of cathodic structural complexity and the nature of constituent materials involved, including lanthanides and group VI B metals and others, has resulted in elaborate fabricative procedures, often with repetitive and reiterative operations. For example, one step common in the conventional art is the masking of passivation layers. Such repetitive or reiterative operations render the conventional art problematic for four related reasons.
With reference to Conventional Art FIG. 6, the steps in a conventional process 600 are presented. In etching cavities for housing the emissive cones (e.g., cathode cones 55; Conventional Art FIGS. 3, 4), a Silicon Nitride (SiNx) inter-layer dielectric (ILD) is attacked by the etchant. To prevent unwanted consumption of this SiNx, a second silicon dioxide (SiO2) passivation layer is masked (step 614), in the conventional art, by blanket coating of photoresistive maskant. This is followed by etching and stripping, deposition of the cathode cones, masking, etching, and stripping of a gate square, deposition of a second ILD layer, and masking, etching, and stripping of a direct via (steps 615 through 619, respectively). The conventional process 600 subsequently configures focus waffles and halos (steps 620-624). As seen in Conventional Art FIG. 6, numerous sets of masking and corresponding etching and related steps and two (2) passivation layers are required to fabricate cathodes for thin CRTs. Further, conventional methods sometimes require photoresist application, and corresponding accompanying process steps, to prevent inordinate consumption of desired passivation layer material during cathode fabrication. This is elaborate, inefficient, and costly. It is especially wasteful in fabricating the M1 and M2 pad areas.
Referring to Conventional Art FIGS. 5B and 5C, composite structures M1PA(C) and M2PA(C) show that a layer PR of photoresist covers a desired passivation layer PAN. This is to prevent unwanted deterioration of the passivation layer PAN in the M1 and M2 pad areas, respectively, during subsequent fabricative processing.
The first problem arising from the conventional art is that the elaborate conventional methods are expensive, individually and cumulatively. Second, the complexity of the conventional art, especially with respect to the relatively large number of steps it requires, consumes inordinate time. Third, this renders the production lines involved correspondingly less efficient and productive than desirable, with correspondingly increased costs. And fourth, the total unit cost of the cathode assembly, and correspondingly, complete thin CRT units, is higher than desirable.
What is needed is a method of fabricating a cathode which reduces the number and/or complexity of steps required conventionally. What is also needed is a method of fabricating a cathode which eliminates one or more passivation layer masking steps, required in the conventional art. Further, what is needed is a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and/or productivity of manufacturing lines engaged in cathode fabrication. Further still, what is needed is a method of fabricating a cathode which reduces the unit cost of thin CRTs manufactured therewith.
The present invention provides, in one embodiment, a method of fabricating a cathode requiring relatively few and somewhat simple steps. In one embodiment, the present invention also provides a method of fabricating a cathode which eliminates a direct via masking step. Further, in one embodiment, the present invention also provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. Further still, the present invention provides, in one embodiment, a method of fabricating a cathode which reduces the unit cost of thin CRTs manufactured therewith.
In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. The process, in one embodiment, involves a number of steps involving technologies well known in the art. Importantly however, in the present embodiment, the requirement for at least one of the direct via masking steps, required by conventional cathode fabrication processes, is eliminated.
The elimination of a direct via masking step in accordance with one embodiment of the present effectively eliminates or substantially reduces costs conventionally associated with executing the step and concomitantly reduces the total time necessary to complete the entire process. Advantageously, this increases production line efficiency and productivity, correspondingly reducing fabrication costs and unit costs of finished devices manufactured therewith.
In another embodiment, the conventional requirement of masking the desired direct vias in the M1 and M2 pad areas with photoresist during etching processes in those areas is eliminated by utilization of one of two novel etchant gas chemistries. Advantageously, this effectuates high etching selectivity, especially between resistor (if used) and Cr conductor layers, and adjustment of Cr metal gate thickness in the M2 area during this etching step. This is not possible with conventional methodology.
These and other advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.